Field of the Invention
The invention relates to a circuit for generating output signals as a function of input signals. The circuit serves as a part of a driver configuration for an output driver and ensures that data are output at an instant when they are regarded as valid.
Output drivers of various types occupy a central function as a component part of integrated semiconductor circuits. As a result of higher clock and data rates in integrated semiconductor circuits, the requirements with regard to the switching speed and a reliable voltage supply are also increasing. The high current pulses at output drivers and at the voltage supply, that are produced in connection with high clock rates and that lead to potential fluctuations in oscillatory systems, can in some instances cause malfunctions in other circuit sections of a semiconductor memory. Oscillatory systems are produced for example by line inductances of leads, bonding wires or lead frames in conjunction with capacitances on the chip.
Problems can arise, in particular, if the signal which enables an output driver and a datum to be applied to the output driver have different propagation times. This problem is present primarily in the case of clocked high-speed memory modules in which the memory access is triggered asynchronously with respect to the clock signal which enables the output driver. If the output driver is enabled too early, there is the risk that the datum to be output is not yet valid and changes its state during the enabled state of the driver. In such a case, a corresponding switching transistor of the output driver switches twice in direct succession, which, at high clock rates even of single switching operations, leads to even higher rates of current rise or in other words steeper current rises. Added to this is the fact that the output driver does not switch from the high-impedance state in the case of the second switching operation, rather at least one switching transistor is already in the on state in other words in the conducting state. In the event of a state change, this switching transistor must be put into the off state as rapidly as possible, which engenders additional current pulses which amplify the above-mentioned effect. The disturbances and irregularities produced in this way result in potential fluctuations at the terminals of the output driver or of the supply voltage which are significantly higher than in the case of a normal, single switching operation.
Attempts have previously been made to limit the rates of current rise which are caused by switching operations of output drivers, and likewise to reduce the inductances on the chip in terms of their magnitude. However, the technical possibilities are limited in this context. In earlier DRAM architectures, in particular fast-page-mode DRAMs and extended-data-out DRAMs with fixed access cycles, a validity signal is generated which enables the output driver only when valid data are present. It is thus ensured that only a single switching operation of the output driver takes place. What this presupposes is a certain memory access time which elapses starting from the triggering of the data access and by which the enabling of the output driver is delayed. In the case of higher and variable frequencies of the access cycle, however, there is the risk that the signal which disables the output driver after a data access and the memory access time overlap temporally, which thus leads to a defective functioning of the output driver. In the case of modern DRAMs (dynamic random access memories), in particular SDRAMs (synchronous DRAMs) and other forms of clocked DRAMs, a temporal overlap of the memory access time and of a clock signal which enables the output driver and disables it again is possible in a certain range. Therefore, a simple control of the data access which stipulates the access cycle and thus the activation of the output driver in terms of instant and duration is no longer appropriate, without there being the risk of multiple switching operations during an access cycle.